Shell, Perl, Verilog, Python, Tcl, Functional and code coverage, Simulation and debugging concepts, Automation scripts, Assertions SVA, UVM methodology, systemverilog

Usb, Tcl, Ethernet, Python, Perl, Pcie, DDR, systemverilog, Uvm, coverage-driven verification, AMBA, digital design RTL understanding, SVA, MIPI

Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Perl, Python, Tcl, DisplayPort, HDMI, MIPI DSI, Uvm, systemverilog

Spi, I2c, Gpio, Uart, Pcie, DDR, UVM methodology, I3C, QSPI, CXL, systemverilog, HBM

code coverage , Nvme, Pcie, Ethernet, System Verilog, DDR, Uvm, Axi, APB, CXL, Industry-standard simulation and debug tools, UCIe, AHB, BFMs, Scoreboards, Checkers, Monitors, Functional coverage, Assertions

UVM (Universal Verification Methodology), SVA (System Verilog Assertions), UPF (Unified Power Format), Git, C, Bug Tracking Tool, System Verilog, Cadence, RTL simulations, Synopsys

Verilog, scripting skills Python, advanced stimulus generation techniques, Uvm, coverage-driven verification, systemverilog