Senior Design Verification Engineer
Senior Design Verification Engineer
Globex Digital CorpEarly Applicant
- Posted 2 months ago
- Be among the first 10 applicants
Job Description
Experience - 7+years
Location - Pan India
NP - Immediate to 60 Days
JD Design Verification
- Understanding the business requirements and functional specifications of the IPs, subsystems and SOC
- Creating Verification Environment Architecture document
- Reviewing and Revising: working towards meeting agreed upon acceptance criteria
- Developing code in System Verilog, UVM (Universal Verification Methodology), C for Unit, Subsystem and SOC level verification
- Performing RTL simulations using Synopsys and Cadence simulators
- Debugging and resolving problems found by simulations .Performance test plan development and maintenance
- Development of transactors, monitors and models for performance verification.
- Implement performance verification flow including monitoring, synchronization, reporting and self-checking mechanisms
- Provide full report of performance metrics and bottlenecks
- Tracking tickets and code releases using Bug Tracking tool and GIT
- Performing UPF (Unified Power Format) based Power Aware simulations
- Coding of Assertion and Functional Coverage bins in SVA (System Verilog Assertions)
- Code & Functional Coverage Closure
- Performing Gate Level simulations .Preparing and conducting reviews of Verification Sign-off documents to ensure SOC tape-out quality
More Info
Key Skills
UVM (Universal Verification Methodology)
RTL simulations
SVA (System Verilog Assertions)
UPF (Unified Power Format)
About Company
Skills:
Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB
Skills:
Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV
Skills:
C, Perl, Python, Fpga, Emulation platforms, Uvm, systemverilog, AMBA bus protocols, Transaction level modeling, Automation scripts, RTL
Skills:
simvision , python, Cadence simulation tools, Uvm, Xcelium, netlist simulation
Skills:
code coverage , Nvme, Pcie, Ethernet, System Verilog, DDR, Uvm, Axi, APB, CXL, Industry-standard simulation and debug tools, UCIe, AHB, BFMs, Scoreboards, Checkers, Monitors, Functional coverage, Assertions