Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

C, Perl, Python, Fpga, Emulation platforms, Uvm, systemverilog, AMBA bus protocols, Transaction level modeling, Automation scripts, RTL

simvision , python, Cadence simulation tools, Uvm, Xcelium, netlist simulation

code coverage , Nvme, Pcie, Ethernet, System Verilog, DDR, Uvm, Axi, APB, CXL, Industry-standard simulation and debug tools, UCIe, AHB, BFMs, Scoreboards, Checkers, Monitors, Functional coverage, Assertions

Cadence Tools, Gate level simulations, VHDL, Formal verification methodologies, VAMS, Testbench creation, Uvm, systemverilog, Motor control for BLDC BSM motor driver devices

Scripting Languages, Sed, Perl, Awk, ASIC design flow, C Assertions coding, ARM based SOC software framework, SV-UVM, UVM assertion based coverage driven verification, constraint random test generation, multi-core multi-layer APIs, functional coverage, ARM processor based SoC architecture, ASIC verification methodologies

C, C++, Vcs, Debugging, RTL simulation, on-chip bus protocols, Xcelium, Uvm, systemverilog, SoC-level verification, AMBA, Axi, APB, Questa, AHB, functional coverage

C, Shell Scripts, JIRA, MATLAB, Git, Perl, Verilog, Python, Tcl, Uvm, systemverilog, Cadence vManager, DSP blocks

Tcl Scripting, Unix Shell Scripting, Perl, Verilog, System Verilog, Debugging, Incisive, IMC, analog mixed signal design, Uvm, advanced verification methodologies, xCelium, vManager, Cadence Virtuoso, test bench development, verification IP, object-oriented programming, Simulation, behavioral modelling, mixed signal verification environment, verification plans, analog blocks