Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm

simvision , python, Cadence simulation tools, Uvm, Xcelium, netlist simulation

Scripting Languages, Sed, Awk, Perl, ARM processor based SoC architecture, ASIC design flow, ASIC verification methodologies, C Assertions coding, multi-core multi-layer APIs, functional coverage, SV-UVM, constraint random test generation, UVM assertion based coverage driven verification, ARM based SOC software framework

Soc Architecture, System Verilog, digital design concepts, UVM Universal Verification Methodology, debugging using waveforms and logs

Asic verification, digital design verification, Uvm, test bench architecture, systemverilog, GIT version control, C Language

Fpga, Logic Design, Verilog, Uvm, Timing Constraints, TCL scripts, regression frameworks, Timing Analysis, Power product design, System-Verilog, RTL Coding, Functional Verification, Sta, micro-architecture, ATPG generation, formal verification, synthesis scripts, Synthesis, ABV, design constraints, Digital Verification, Scan Insertion

Usb, System Verilog, Jtag, Ethernet, Python, Pcie, Perl, TSN, UVM methodology, SoC architecture verification, scripting in Linux Unix environments, High speed USB, Design for Debug, ARM based SoC verification