Senior Design Verification Engineer
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•5 Years of ASIC SoC Verification Experience
• Expertise in SV-UVM, C, Assertions coding
• Must have good understanding of ARM processor based SoC architecture and must have completed verification of two or more embedded processor based SoC
• Must have expertise in on ASIC verification methodologies and ASIC design flow.
• Have expertise on ARM based SOC software framework (multi-core multi-layer APIs)
• Proven experience of the design verification methodologies such as UVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation
• Strong problem solving/debugging skills
• Experience on working in SOC with complex Analog-Digital Interface will be considered as advantage.
• Experience on working in SOC with WREAL/AMS model will be considered as advantage
• Experience in Scripting Languages like Perl, awk, sed, will be an advantage
Job ID: 116788413
Skills:
Jasper, Perl, Python, Asic verification, formal property checking tools, Synopsys Magellan, systemverilog, Cadence IEV, verification methodologies and tools, VC Formal, functional coverage, SVA
Skills:
Jasper, Perl, Python, Asic verification, verification methodologies, Synopsys Magellan, Uvm, systemverilog, Cadence IEV, VC Formal, functional coverage, SVA
Skills:
Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA
Skills:
Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification
Skills:
Verilog, Tcl, Python, Perl, Uvm, VHDL, systemverilog
