Jasper, Perl, Python, Asic verification, formal property checking tools, Synopsys Magellan, systemverilog, Cadence IEV, verification methodologies and tools, VC Formal, functional coverage, SVA

Jasper, Perl, Python, Asic verification, verification methodologies, Synopsys Magellan, Uvm, systemverilog, Cadence IEV, VC Formal, functional coverage, SVA

Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA

Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification

Verilog, Tcl, Python, Perl, Uvm, VHDL, systemverilog

Tcl, Python, Perl, Vcs, Uvm, Questa, systemverilog, Verdi

code coverage , Nvme, System Verilog, Ethernet, Pcie, DDR, Uvm, UCIe, simulation and debug tools, AHB, assertions, functional coverage, CXL, APB, Axi