Senior Design Verification Engineer
- Posted 3 months ago
- Be among the first 10 applicants
Job Description
GFx IP Verification Engineer
Job Description:
- Develop and maintain UVM-based verification environments for Graphics (GFx) IP blocks.
- Create comprehensive test plans based on design specifications and architecture.
- Execute simulations, analyze waveforms, and debug functional issues.
- Work closely with design and architecture teams to validate GPU/display pipeline components.
- Strong experience in SystemVerilog, UVM, and scripting (Python/Perl/TCL).
- Exposure to graphics standards such as HDMI, DisplayPort, or MIPI DSI is preferred.
- Perform coverage analysis and ensure thorough validation of corner cases.
- Familiarity with performance modeling, power-aware verification, or emulation is a plus.
Experience: 4+ Years.
Location: Bengaluru / Hyderabad.
Notice Period: 30 Days only.
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Key Skills
About Company
Skills:
Cadence Tools, Gate level simulations, VHDL, Formal verification methodologies, VAMS, Testbench creation, Uvm, systemverilog, Motor control for BLDC BSM motor driver devices
Skills:
SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification
Skills:
Vcs, Pcie, Python, Tcl, Xcelium, Uvm, systemverilog, APB, Questa, AXI4, AHB, SVA
Skills:
Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage
Skills:
Vcs, Shell, Perl, Python, Verdi, Assertions SVA, Verification planning, RISC-V, Regression and debug, UVM testbenches, Uvm, systemverilog, Test-plan development, Functional and code coverage, DDR verification, Questa