Senior RTL Engineer

. Experience Required: 7-12 years

. Technical Requirements:

o Strong System Verilog and Verilog coding skills

o Knowledge of specific IP domains:

. Memory Engineers: DDR4/5 controllers, cache controllers, memory interfaces

. I/O Engineers: UART, SPI, I2C, GPIO, SD/MMC controllers

. Network Engineers: Ethernet MAC, network protocols

. Security Engineers: AES, SHA, RSA, TRNG implementation

. System Engineers: Interrupt controllers, timers, DMA

o Understanding of synthesis and timing constraints

o Understanding of CDC

o Debug and verification support capabilities

o Documentation and coding standard compliance

. Key Responsibilities:

o IP wrapper development and customization

o RTL coding for custom logic blocks

o Interface protocol implementation

o RTL debugging and issue resolution

o Code reviews and quality assurance

o Technical documentation