S
SENIOR ENGINEER, DESIGN AUTOMATION METHODOLOGIES
S
SENIOR ENGINEER, DESIGN AUTOMATION METHODOLOGIES
semiconductor engineering5-7 Years
- Posted 10 days ago
- Be among the first 10 applicants
Job Description
We are seeking a highly skilled and technically proficient Engineer with experience in ASIC front-end methodologies across IP and SoC design domains. The ideal candidate will bring over 5+ years of VLSI experience, having successfully handled and deployed sophisticated automation flows, design checks and collaborated effectively to deliver innovative solutions in the semiconductor domain. The role includes working with global design teams and internal collaborators to deploy IP/SoC design checks, integration methodologies and improve them continuously.
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Key Skills
About Company
Skills:
Vc, Perl, Verilog, Python, System Verilog, Tcl, LINT, cdc, Vlsi, front-end design verification techniques, formal verification tools, LEC, spyglass, FV, Synthesis, RDC, Design Compilers, EDA Tools, ASIC Design
Skills:
Verilog, Usb, Tcl, Arm, System Verilog, Ethernet, Perl, Spi, I2c, Python, Soc Architecture, LINT, ASIC design flow, Timing Analysis, peripheral IPs, Synthesis, Low-power design, Axi, power estimations, BUS Protocols, MBIST, Bus Matrix design, MIPS, AMBA, Rtl Design, timing constraint SDC, DFT concepts, RDC, Formal CDC
Skills:
JIRA, Jenkins, Analyzing verification issues, Intel Quartus, Xilinx Vivado, FPGA design and verification following the DO-254 process, Interpreting schematics and layout diagrams, RTL design using VHDL, Electronic components and circuit design flow, Microchip Libero SoC
Skills:
Bonding System, CYMCAP, HV cable design, Earth Continuity, Project management, Installation testing and maintenance, Co-Axial Cable, Short circuit calculations, Cable sizing and insulation specifications, Report Preparation, Technical problem-solving, Site surveys and assessments, Compliance with standards and regulations, Quality control checks, Cable Modelling Software, Health Safety compliance, Cable Bonding layout
Skills:
Place and route (PnR), System on Chips (SoCs), Static Timing Analysis (STA), Unified Power Format (UPF), Deep sub-micron technology, Multi-voltage domains, Physical design methodologies, Circuit Design, Power gating, IP integration, Netlist2GDS, ASIC design flows, Sign-off optimizations, Multiple technology nodes in advanced processes, device physics, Floorplan, Sign-off convergence, Lower technology nodes, Low power design implementation