Vc, Perl, Verilog, Python, System Verilog, Tcl, LINT, cdc, Vlsi, front-end design verification techniques, formal verification tools, LEC, spyglass, FV, Synthesis, RDC, Design Compilers, EDA Tools, ASIC Design

Verilog, Usb, Tcl, Arm, System Verilog, Ethernet, Perl, Spi, I2c, Python, Soc Architecture, LINT, ASIC design flow, Timing Analysis, peripheral IPs, Synthesis, Low-power design, Axi, power estimations, BUS Protocols, MBIST, Bus Matrix design, MIPS, AMBA, Rtl Design, timing constraint SDC, DFT concepts, RDC, Formal CDC

JIRA, Jenkins, Analyzing verification issues, Intel Quartus, Xilinx Vivado, FPGA design and verification following the DO-254 process, Interpreting schematics and layout diagrams, RTL design using VHDL, Electronic components and circuit design flow, Microchip Libero SoC

Bonding System, CYMCAP, HV cable design, Earth Continuity, Project management, Installation testing and maintenance, Co-Axial Cable, Short circuit calculations, Cable sizing and insulation specifications, Report Preparation, Technical problem-solving, Site surveys and assessments, Compliance with standards and regulations, Quality control checks, Cable Modelling Software, Health Safety compliance, Cable Bonding layout

Place and route (PnR), System on Chips (SoCs), Static Timing Analysis (STA), Unified Power Format (UPF), Deep sub-micron technology, Multi-voltage domains, Physical design methodologies, Circuit Design, Power gating, IP integration, Netlist2GDS, ASIC design flows, Sign-off optimizations, Multiple technology nodes in advanced processes, device physics, Floorplan, Sign-off convergence, Lower technology nodes, Low power design implementation

C, Perl, Verilog, Gdb, Python, Indago, SOC design, Cadence

power delivery , Test Plans, Firmware, automation, Logic Design, AI-enabled debug, thermal dependencies, Debug, system-stress campaigns, multi-unit fleet testing, software interaction, System Validation, platform programs, cross-functional alignment, Signal Integrity, PVT stress, NVIDIA GPU SoC, validation workflows