Q
SoC Physical Design Engineer, Senior Staff
Q
SoC Physical Design Engineer, Senior Staff
Qualcomm4-12 Years
- Posted 14 hours ago
- Be among the first 10 applicants
Job Description
Company
Qualcomm India Private Limited
Job Area
Engineering Group, Engineering Group > Hardware Engineering
General Summary
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
If you would like more information about this role, please contact Qualcomm Careers.
Qualcomm India Private Limited
Job Area
Engineering Group, Engineering Group > Hardware Engineering
General Summary
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
- Bachelor's or Master's degree from a top-tier institute.
- 12 years of experience in physical design from product-based companies.
- Proven experience in managing complex subsystems and small teams.
- Proficiency in complete Netlist2GDS: Floorplan, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.
- Hand on experience in lower technology nodes.
- Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration.
- Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating.
- Familiarity with ASIC design flows and physical design methodologies.
- Strong understanding of circuit design, device physics, and deep sub-micron technology.
- Experience working on multiple technology nodes in advanced processes.
- Proficiency in automation to drive improvements in PPA.
- Managing and driving a small team for project execution and PPA targets
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
If you would like more information about this role, please contact Qualcomm Careers.
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
Deep sub-micron technology
Multi-voltage domains
Physical design methodologies
Power gating
Place and route (PnR)
IP integration
Netlist2GDS
ASIC design flows
Sign-off optimizations
System on Chips (SoCs)
Multiple technology nodes in advanced processes
Sign-off convergence
Lower technology nodes
Low power design implementation
Static Timing Analysis (STA)
Unified Power Format (UPF)
About Company
Skills:
hardware engineering , Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, PNR, device physics, Low power design implementation
Skills:
circuit architectures, chip-level reliability considerations, simulation methodologies, power management ICs, analog circuit design fundamentals, transistor-level analog IC design, ESD latch-up, analog IP development, analog layout techniques
Skills:
Clp, Soc Architecture, Verilog, System Verilog, LINT, physical design constraints, cdc, DFT methodologies, AMBA protocols, Convergence, UPF, FPGA Prototyping, Rtl Design, PTPX power analysis, Axi, Emulation, APB, low-power methodologies, Microarchitecture, AHB
Skills:
Ecos, Perl, Python, Tcl, FC PrimeTime, Sta, Design Compiler, CTS, EM, physical signoff, Ir, advanced-node SoCs, congestion optimization, ASIC Physical Design Full-Chip Implementation, MCMM, design closure, low-power implementation, PPA trade-offs, Synopsys ICC2
Skills:
Rtl Design, high-speed interfaces, thermal monitoring integration, power management, clock-gating, micro-architecture, systemverilog, embedded microcontroller integration, reset-domain architecture