Senior DFT Engineer
- Posted 2 months ago
- Be among the first 10 applicants
Job Description
Senior DFT Engineer
Job Description
- PDL: Writing ICL and PDL by Own
- Debug protocols: Strong understanding on Jtag 1149.1-2013, ijtag - P1687
- Debug patterns exposure: .V, optional STIL or SVF
- SSN + SSH architecture understanding.
- Tessent tool exposure: TestKompress, Tessent shell
- Scripting: TCL, shell
Optional Skills (Good to have)
- SCAN architecture, past TAP/JTAG related DV feature.
- Patterns re-targetting
- Good Debug skills on the same.
Experience: 4 to 5 Years
Location: Bangalore
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
SSN
ijtag - P1687
TCL shell
.V optional STIL
Jtag 1149.1-2013
SVF
SSH architecture understanding
Tessent shell
Debug protocols
Debug patterns exposure
PDL Writing
Tessent tool exposure
About Company
Skills:
perl, Vcs, Jtag, shell scripting, Awk, Design Compiler, Verdi, Fusion Compiler, BIRA, NCSim, MBIST, Tessent, ATPG, TetraMax Tool, BISR, Modelsim, Tester scan
Skills:
Scan Compression Techniques, Fault Models, DFT Tools, Sign-Off, Scripting Automation, DFT Implementation, Boundary Scan IEEE 1149.1, Test Coverage Optimization, Post-Silicon Validation
Skills:
Unix, Svn, Shell, Report Automation, Linux, Verilog, Tcl, Python, Perl, Git, Cadence Modus, MBIST, Scan compression, Scan architecture, log parsing, TestMAX, systemverilog, ATPG, DFT fundamentals, TetraMax, Synopsys DFT Compiler, LBIST, flow orchestration
Skills:
Dft, SSN, Simulation, Synopsys, Scan Insertion, Memory BIST, ATPG, DRC Coverage, Sms, pdl, IJTAG, ICL, Debug, occ, TetraMax
Skills:
Test insertion and verification, DFT concepts, Yield improvement, MBIST, Coverage improvement, Post silicon debug, Tessent Shell, ATPG, Mentor Graphics DFT tools, Pattern generation, Vector simulation, IJTAG, DFT Architecture