perl, Vcs, Jtag, shell scripting, Awk, Design Compiler, Verdi, Fusion Compiler, BIRA, NCSim, MBIST, Tessent, ATPG, TetraMax Tool, BISR, Modelsim, Tester scan

Scan Compression Techniques, Fault Models, DFT Tools, Sign-Off, Scripting Automation, DFT Implementation, Boundary Scan IEEE 1149.1, Test Coverage Optimization, Post-Silicon Validation

Unix, Svn, Shell, Report Automation, Linux, Verilog, Tcl, Python, Perl, Git, Cadence Modus, MBIST, Scan compression, Scan architecture, log parsing, TestMAX, systemverilog, ATPG, DFT fundamentals, TetraMax, Synopsys DFT Compiler, LBIST, flow orchestration

Dft, SSN, Simulation, Synopsys, Scan Insertion, Memory BIST, ATPG, DRC Coverage, Sms, pdl, IJTAG, ICL, Debug, occ, TetraMax

Test insertion and verification, DFT concepts, Yield improvement, MBIST, Coverage improvement, Post silicon debug, Tessent Shell, ATPG, Mentor Graphics DFT tools, Pattern generation, Vector simulation, IJTAG, DFT Architecture

boundary scan , Perforce, Jtag, Git, Perl, Tcl, Verilog Hdl, Synopsys SMS SHS flow, Scan DRC flows, Mentor, Cadence, Siemens Tessent, AT-Speed SCAN, Dft, ATE silicon debug, EDA Tools, IJTAG, Multimedia subsystems DFT, MBIST, Shell flow, IO BIST, ATPG, Stuck-AT, Synopsys

Dft, SDC, ATPG, Scan, MBIST, SSN, GLS

ATPG (Automatic Test Pattern Generation), logic bist , test coverage , Memory BIST (MBIST), DFT architecture, Digital DFT, Scan compression, SoC MCU architecture, DFT protocols, Debug effort