Dft, SDC, ATPG, Scan, MBIST, SSN, GLS

Perl, Python, Tcl, scan compression, BSCAN, Simulation, MBIST, DFT insertion, ATPG, LBIST, pattern generation, IJTAG

Test insertion and verification, DFT concepts, Yield improvement, MBIST, Coverage improvement, Post silicon debug, Tessent Shell, ATPG, Mentor Graphics DFT tools, Pattern generation, Vector simulation, IJTAG, DFT Architecture

boundary scan , Debugging, Tessent tools, coverage analysis, clock analog observe PLL RO, DFT – Scan ATPG, thermal sensors, SSN EDT, JTAG networks, DFX DV for IP debug units, TDR verification, clock-stop features, scan pattern generation, test-case development, AFM fault models, scan pattern simulation, root-cause analysis

boundary scan , Perforce, Jtag, Git, Perl, Tcl, Verilog Hdl, Synopsys SMS SHS flow, Scan DRC flows, Mentor, Cadence, Siemens Tessent, AT-Speed SCAN, Dft, ATE silicon debug, EDA Tools, IJTAG, Multimedia subsystems DFT, MBIST, Shell flow, IO BIST, ATPG, Stuck-AT, Synopsys

perl, Vcs, Jtag, shell scripting, Awk, Design Compiler, Verdi, Fusion Compiler, BIRA, NCSim, MBIST, Tessent, ATPG, TetraMax Tool, BISR, Modelsim, Tester scan

Scan Compression Techniques, Fault Models, DFT Tools, Sign-Off, Scripting Automation, DFT Implementation, Boundary Scan IEEE 1149.1, Test Coverage Optimization, Post-Silicon Validation

Gate Level Simulations, stuck-at transition, Scan Insertion, memory repair solutions, MBIST, JTAG boundary scan, bridge path delay, DFT architecture, EDA Tools, DRC, IEEE 1149.1, ATPG pattern generation, scan chain stitching, DFT rule checks

Python, Perl, Logic Design, Uvm, Post Silicon Testing, SV, DFT Engineering, Architecture Verification, Constrained random testing, Profiling Tools, Coverage metrics