C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation

Tcl, Python, Logical Equivalence, Synthesis, Timing Analysis, Physical Verification DRC LVS ERC, Physical design flows, Place And Route, EDA Tools, Budgeting, floorplanning, Clock CTS

power integrity , Routing, Synthesis, Multi-Voltage Domains, Sign-off, Physical Design implementation, Placement, Low-Power Design, Physical Verification, Timing Closure, floorplanning, CTS

Tcl, Routing, Perl, 28nm and lower technology nodes, Timing Constraints, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, Methodologies, CTS, Innovus, Sta, ICC2, Tk, Placement, Timing Closure, PT-PX, sub-micron technology, Netlist2GDSII Implementation

Physical Design, Physical Design Engineer, Automation script

Tcl, Cursor, Python, RTL-to-GDSII flow, AI concepts, Claude, layout closure, timing convergence, Cadence Innovus, Place And Route, AI technologies, design implementation, Physical Design, Synopsys ICC2, Codex, Synthesis, standard place-and-route flows, tool-specific scripting, Clock Tree Synthesis

Network-on-Chips (NoC, Multi-mode multi-corner (MMMC timing closure, Physical design implementation, Synthesis, System IP components, Timing Closure, Sign-off, Coherent CPU clusters, floorplanning, Uncore subsystems, Place-and-route, Partitioning, RTL-to-GDSII implementation, Timing budgeting, Hierarchical design techniques