Senior Physical Design Engineer
Senior Physical Design Engineer
leadsoc technologies pvt ltd- Posted 14 days ago
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Job Description
Senior Physical Design Engineer
Exp-3-6yrs
Location-Bengaluru
Job Description:-
- Physical Design Implementation and Methodology: Engage in the implementation of physical design, develop methodologies, and manage sign-off processes.
- Core Design Tasks: Execute floorplanning, clock planning, placement and routing, timing closure, and physical verification to ensure design integrity and performance.
- Project Management: Oversee project schedules, troubleshoot design and workflow issues, and drive methodological improvements and execution strategies.
- Collaborative Teamwork: Work collaboratively with team members to successfully complete projects within designated timelines.
- Programming Skills: Utilize programming skills to effectively complete tasks, with a focus on scripting and automation to enhance workflow efficiency.
- Proficiency in EDA Tools: Demonstrate proficiency in using Electronic Design Automation (EDA) tools such as Innovus, ICC2, LEC, PrimeTime, Calibre, among others.
Requirement:-
- Familiarity with EDA Tools: Proficient in using EDA tools such as ICC, ICCII, and INNOVUS.
- ASIC Flow Knowledge: Well-versed in the ASIC design flow.
- Programming Skills: Proficient in Tcl, Perl, scripting, C, and C++ programming languages.
- Strong Communication Skills: Excellent communication abilities.
- Proactive and Responsible: Highly proactive, enthusiastic, and responsible.
- Large-Scale Design Experience: Experience handling designs with more than 2 million instance counts is preferred.
- Top-Level Physical Design and Advanced Node Experience: Experience in top-level physical design and advanced node tapeout is highly desirable.
More Info
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Key Skills
Clock Planning
Placement and Routing
Physical Design Implementation
About Company
Skills:
power integrity , Perl, Python, Tcl, physical design sign-off, static dynamic IR drop, physical ECOs, Cadence Voltus, electromigration, power-grid optimization, PG strengthening, Ansys RedHawk, EM IR analysis, vectorless EM IR analysis
Skills:
Tcl, Python, Logical Equivalence, Synthesis, Timing Analysis, Physical Verification DRC LVS ERC, Physical design flows, Place And Route, EDA Tools, Budgeting, floorplanning, Clock CTS
Skills:
power integrity , Routing, Synthesis, Multi-Voltage Domains, Sign-off, Physical Design implementation, Placement, Low-Power Design, Physical Verification, Timing Closure, floorplanning, CTS
Skills:
Tcl, Python, PERL, ECO Timing Closure, Synthesis, Layout Closure, Block-level and Full-chip Floor-planning, primetime, Ir, Physical Verification, Innovus, CTS, Sta, ICC2, Physical Design, Tempus, RTL2GDSII flow, Seahawk, Place And Route, Timing Convergence, High Frequency Design Methodologies
Skills:
Tcl, Routing, Perl, 28nm and lower technology nodes, Timing Constraints, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, Methodologies, CTS, Innovus, Sta, ICC2, Tk, Placement, Timing Closure, PT-PX, sub-micron technology, Netlist2GDSII Implementation