Senior Physical Design Engineer
Senior Physical Design Engineer
Globalfoundries Engineering Private Limited4-6 Years
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Job Description
Your Job
The engineer will be responsible for doing physical design implementation, timing closure, and Physical verification at the block level.
Job Responsibilities
- Execute block-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs.
- Schematic (LVS) checks, Antenna checks. Need experience in full chip physical design such as integration of blocks, top level floorplanning, clock tree synthesis, timing constraints development and convergence. I/O placement and constraints.
- Experience with UPF coding and modification as per design requirements. Need to take care of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out.
- Should be able to interface with the Front End Design team to resolve Design Issues Must possess hands on experience in P&R from RTL to GDS including timing closure and Physical verification. Design experience in all aspects of physical design.
- Proficient and powerful user of Synopsys ICC/ICC2, Cadence innovus. Experience in Mentor Calibre tools to run Physical verification Experience in Apache to run EM IR- analysis is a Plus.
- Experience in Tcl/ Tk, PERL, Makefile is a Plus Excellet verbal and written communication skill is required.
- Excellent interpersonal and analytical skills with an ability to work independently and within a team are required. Highly motivated, excellent team player, and customer oriented.
Experience
- 4-6 Years of Physical Design Experience
Qualification
- Bachelor or Master's degree in Electrical and Electronics engineering.
Required Skills And Qualification
- Good understanding of low power concepts. Good exposure in Floorplanning, CTS, STA, Physical Verification.
- Good understanding of top-level physical design, partitioning and timing constraints, IR Drop.
- Basic understanding of timing constraints.
- Knowledge in Automation script (TCL, Perl, etc), Auto FuSA would be an added advantage.
More Info
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Key Skills
About Company
GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.
Skills:
hardware engineering , Deep sub-micron technology, ASIC design flows, Physical design methodologies, Circuit Design, device physics, Floorplan, Netlist2GDS
Skills:
power optimization , Routing, Logic Design, Perl, Python, Tcl, Circuit Design, floorplanning, Mentor, Cadence, Signal Integrity, LVS, Digital Design Fundamentals, Physical Verification, Physical Design, ERC, Placement, Timing Closure, DRC, Timing, EDA Tools, Synopsys, Rtl Design
Skills:
clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff
Skills:
C, Tcl, Routing, Perl, Physical Verification, LEC, Calibre, Innovus, floorplanning, EDA Tools, Clock Planning, ICC2, primetime, Placement, Timing Closure, Physical Design Implementation
Skills:
Tcl, Python, PERL, Seahawk, Synthesis, ECO Timing Closure, Layout Closure, Block-level and Full-chip Floor-planning, primetime, Physical Verification, Ir, CTS, Innovus, Sta, ICC2, Physical Design, Tempus, RTL2GDSII flow, Place And Route, Timing Convergence, High Frequency Design Methodologies