Senior Physical Design Engineer
- Posted 12 days ago
- Be among the first 10 applicants
Job Description
Purpose:
As a Senior SoC Physical Design Implementation, the role includes working on the SoC/Subsystem level RTL2GDS Implementation with aligned PPA & Power/DRC Signoff as per PDK requirements. The role also oversee the Implementation strategy with Signoff Analysis, Timing/LV/EM/IR Analysis/ESD Analysis with driving methodology and commanding tools with flow. Collaboration as partner with Frontend and Packaging Teams/Full Chip Integration Teams. This position involves technical expertise and problem-solving skills to manage the estimation and project effectively.
Experience: 6 to 11 years
Responsibilities:
- Leadership:
- Manage the Physical Design of Top/SS/Partitions, ensuring alignment with the overall project and company objectives.
- Mentor and develop team members, fostering a culture of excellence, collaboration, and continuous learning.
- Coordinate cross-functional teams including RTL designers, verification engineers, and post-silicon teams to ensure seamless sign-off processes.
2 Physical Design Integration & Implementation:
- Develop and implementation strategies that ensure the quality and reliability of physical designs.
- Establish and enforce methodologies, best practices, and checklists for BE Integration/PNR/Floor Plan/Power Mesh/Clocking/Power integrity, Signal Integrity, Timing Signoff DRC/LVS clean-up, and other sign-off criteria.
- Adoption of the latest tools, technologies, and methodologies to improve sign-off efficiency and effectiveness.
3 Technical Oversight:
- Provide expert guidance in resolving complex sign-off issues related to PNR, and timing/physical verification.
- Analyze and resolve any bottlenecks in the physical design process, ensuring design meets all performance, area, and power requirements.
- Collaborate closely with the design and verification teams to ensure that the physical design is sign-off ready.
- Collaboration with EDA:
- Collaborate EDA tool vendors, ensuring the company's needs are met about tool features, enhancements, and support.
- Evaluate and recommend new tools and methodologies for physical design and sign-off.
5 Quality:
- Ensure that all designs meet the required quality standards before sign-off, including thorough verification of timing, power, and physical integrity. Implement robust quality control measures to ensure zero-defect silicon and first-time-right success.
6 Compliance and Standards:
- Ensure compliance with industry standards and regulatory requirements during the sign-off process.
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
LV EM IR Analysis
ESD Analysis
Physical Design Integration
RTL2GDS Implementation
PPA Power DRC Signoff
LVS clean-up
DRC
PNR Floor Plan
Power Mesh
Timing Signoff
About Company
Skills:
power optimization , Routing, Logic Design, Perl, Python, Tcl, Circuit Design, floorplanning, Mentor, Cadence, Signal Integrity, LVS, Digital Design Fundamentals, Physical Verification, Physical Design, ERC, Placement, Timing Closure, DRC, Timing, EDA Tools, Synopsys, Rtl Design
Skills:
Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology
Skills:
Place and route (PnR), System on Chips (SoCs), Static Timing Analysis (STA), Unified Power Format (UPF), Deep sub-micron technology, Multi-voltage domains, Physical design methodologies, Circuit Design, Power gating, IP integration, Netlist2GDS, ASIC design flows, Sign-off optimizations, Multiple technology nodes in advanced processes, device physics, Floorplan, Sign-off convergence, Lower technology nodes, Low power design implementation
Skills:
redhawk , Shell, PERL, Verilog, Tcl, place and route methodologies, low power physical design flows and methodologies, Fusion Compiler, physical implementation and analysis tools, timing and signal integrity analysis, Innovus, Calibre, VHDL, power integrity and reliability analysis, power grid planning and implementation, Starrcxt, timing optimization and timing closure, placement and optimization, metal-only ECO implementation, floorplan exploration and optimization, Clock Tree Synthesis
Skills:
redhawk , Verilog, Fusion Compiler, Metal-only ECO Implementation, Timing Optimization, Signal Integrity Analysis, FLASH Process Technologies, Floorplan Exploration, Innovus, Calibre, low power design, GDSII Flow, VHDL, Physical Design, Starrcxt, Reliability Analysis, Clock Tree Synthesis