Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Shell, Perl, Verilog, Python, Tcl, Functional and code coverage, Simulation and debugging concepts, Automation scripts, Assertions SVA, UVM methodology, systemverilog

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Usb, Tcl, Ethernet, Python, Perl, Pcie, DDR, systemverilog, Uvm, coverage-driven verification, AMBA, digital design RTL understanding, SVA, MIPI

Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Test Plan Creation, Debugging, Python, Perl, VIP integration, testbench architecture, Uvm, verification methodologies, scoreboarding, systemverilog, coverage-driven verification, execution and review, assertions, regression management, debug flows, functional coverage

C, Perl, Python, Fpga, Emulation platforms, Uvm, systemverilog, AMBA bus protocols, Transaction level modeling, Automation scripts, RTL

Shell, Perl, Python, Tcl, Debugging RTL verification issues, Assertions SVA, SoC IP architecture and verification methodologies, UVM methodology, systemverilog, Functional Verification, Coverage-driven verification

Noc, Usb, Pcie, Uart, I2c, Spi, cdc, Network on Chip, AMBA protocols, SoC IP Design

cache coherency , Uvm, DMA engines, ARM-based SoCs, memory systems, systemverilog, Transaction-level verification, CHI, Ace, AXI NoC architectures