Senior Design Verification Engineer
Senior Design Verification Engineer
ALTEN Calsoft Labs- Posted 2 months ago
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Job Description
Job Opening: SoC Design Verification Engineer (IP Verification)
Experience: 10+ Years
We are seeking a highly skilled SoC Design Verification Engineer with strong expertise in IP and Sub-system level verification using SystemVerilog and UVM. The ideal candidate will play a key role in ensuring functional correctness and quality of complex SoC designs.
Key Responsibilities & Requirements:
- Hands-on experience in SoC-level and IP-level verification, including VIP integration, coverage-driven verification, and debugging
- Strong proficiency in SystemVerilog/UVM testbench architecture, including assertions, scoreboarding, and functional coverage
- Experience in IP and sub-system verification, including test plan creation, execution, and review
- Solid understanding of verification methodologies, regression management, and debug flows
- Proficiency in scripting languages such as Python or Perl for automation and regression support
- Ability to collaborate effectively with design, architecture, and cross-functional teams
- Strong analytical, problem-solving, and communication skills
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
VIP integration
testbench architecture
verification methodologies
scoreboarding
coverage-driven verification
execution and review
assertions
regression management
debug flows
functional coverage
About Company
Skills:
Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB
Skills:
Shell, Perl, Verilog, Python, Tcl, Functional and code coverage, Simulation and debugging concepts, Automation scripts, Assertions SVA, UVM methodology, systemverilog
Skills:
Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog
Skills:
Usb, Tcl, Ethernet, Python, Perl, Pcie, DDR, systemverilog, Uvm, coverage-driven verification, AMBA, digital design RTL understanding, SVA, MIPI
Skills:
Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV