Senior Design Verification Engineer
Senior Design Verification Engineer
smartsoc solutions pvt ltd- Posted 2 months ago
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Job Description
Required Experience
- 5+ years of hands-on ASIC / SoC Design Verification experience
- Strong experience with SystemVerilog & UVM
- Hands-on verification experience in any one or more of the following protocols:
- PCIe / PCI Express
- DDR / LPDDR
- MIPI
- SerDes
- USB
- Ethernet
- CXL
- UCIe
- High-Speed Interconnect / Data Transfer Protocols
Key Responsibilities
- Develop and execute functional verification strategies for complex ASIC/SoC designs.
- Develop SystemVerilog/UVM testbenches, test scenarios and verification environments.
- Create test plans, test cases, functional coverage and assertions.
- Perform debugging and root-cause analysis using simulation and waveform tools.
- Work closely with RTL Design, Architecture and SoC teams to identify and resolve design issues.
- Drive verification from test planning through coverage closure and sign-off.
- Participate in IP, subsystem and SoC-level verification.
More Info
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Key Skills
About Company
Skills:
Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB
Skills:
Unix, Makefile, Configuration Management, Shell, PERL, System Verilog, Python, ARM CPU, PCI Express, verification dashboarding tools, Uvm, AMBA bus protocols, Ethernet bus protocols
Skills:
Shell, Perl, Verilog, Python, Tcl, Functional and code coverage, Simulation and debugging concepts, Automation scripts, Assertions SVA, UVM methodology, systemverilog
Skills:
Usb, Tcl, Ethernet, Python, Perl, Pcie, DDR, systemverilog, Uvm, coverage-driven verification, AMBA, digital design RTL understanding, SVA, MIPI
Skills:
Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV