R&D Engineer IC Design

Job Description:

The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)s designs – DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.

The candidate should have in-depth knowledge of DFT concepts and should be well experienced in various aspects of DFT -ATPG, MBIST & JTAG. The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug. Strong problem solving & debugging skills are a must. Expertise in scripting languages such as perl, shell, etc. is an added advantage. Experience with either Seimens-Mentor Graphics DFT tools (TestKompress, Fastscan) is highly desirable.

The candidate should have worked with team across multiple geographies. The candidate should be able to handle his/her work independently and also supervise the work of other team members as required. The candidate should possess excellent communication skills.

Educational qualification & Experience Level : Bachelor's degree with 8+ years of relevant experience or Master's degree with 6+ years of relevant experience

R027601