Physical Design Engineer
- Posted 9 days ago
- Be among the first 10 applicants
Job Description
-This role requires a senior-level Physical Design Engineer (5–8years) with end-to-end ownership of block-level PnR and signoff on advanced nodes.
-The engineer is expected to independently drive floor planning, placement, CTS, routing, extraction, STA, and EM/IR closure, consistently meeting aggressive PPA targets for SoC designs.
-The candidate should have proven experience across multiple advanced technology nodes, deep understanding of ASIC PD methodologies, and solid digital design fundamentals.
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Key Skills
CTS
ASIC PD methodologies
digital design fundamentals
EM IR closure
signoff
About Company
Skills:
ML optimization tools (DSO.ai), CTS and routing, Timing-driven placement, PPA Optimization, floorplanning, Hierarchical physical design, RTL-to-GDS implementation flow, Synopsys Fusion Compiler, Pin assignment, Timing budgeting
Skills:
Physical Design, Timing Closure, Power Planning, Deep sub-micron technology issues, Floor Planning, Signal integrity analysis, Place And Route
Skills:
Ecos, Perl, Tcl, Python Scripting, Sta, CTS, Cadence Innovus, routing optimization, congestion optimization, SDC, MMMC, advanced technology nodes, full-chip physical implementation, constraint development, floorplanning, PPA improvements, Timing Analysis, setup hold closure, SI crosstalk, Timing Closure, complex SoC designs, Placement, Power Planning
Skills:
Tcl Scripting, Shell scripting, Python, Routing, Perl, Sta, Signoff, CTS, OCV, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, LVS, Signal Integrity, IR Drop, Physical Verification, MCMM, POCV, Setup Hold, RTL-to-GDSII Physical Design flow, floorplanning, Post-route Optimization, Placement Optimization, EM, Power Planning, Eco, Timing Closure, DRC, AOCV, Synopsys ICC2
Skills:
Clp, Sta, Timing Constraints, RTL synthesis, LEC, low-power design concepts