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Physical Design Engineer
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- Posted 19 days ago
- Be among the first 30 applicants
Job Description
Description
We are seeking an experienced Physical Design Engineer to join our team in India. The ideal candidate will have a strong background in physical design implementation and will be responsible for optimizing IC layouts to meet performance and power requirements.
Responsibilities
- Perform physical design implementation of integrated circuits (ICs) from RTL to GDSII.
- Develop and optimize physical layouts for performance, power, and area.
- Conduct design rule checks (DRC) and layout versus schematic (LVS) verification.
- Collaborate with design engineers to resolve issues related to physical design.
- Utilize EDA tools for various stages of the physical design flow, including synthesis, place and route, and timing analysis.
- Engage in design reviews and provide feedback to ensure adherence to design specifications.
Skills and Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 6-15 years of experience in physical design engineering or a related field.
- Proficiency in using EDA tools such as Cadence, Synopsys, or Mentor Graphics.
- Strong understanding of VLSI design principles and physical design methodologies.
- Experience with RTL synthesis and timing closure techniques.
- Familiarity with scripting languages such as Tcl, Perl, or Python for automation.
- Excellent problem-solving skills and attention to detail.
- Ability to work collaboratively in a team environment.
Bachelor Of Technology (B.Tech/B.E), Masters in Technology (M.Tech/M.E)
More Info
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Key Skills
About Company
Skills:
Routing, Physical Verification, Physical Design, EDA Tools, floorplanning, Placement, Timing Closure, DRC, LVS
Skills:
ML optimization tools (DSO.ai), CTS and routing, Timing-driven placement, PPA Optimization, floorplanning, Hierarchical physical design, RTL-to-GDS implementation flow, Synopsys Fusion Compiler, Pin assignment, Timing budgeting
Skills:
Physical Design, Timing Closure, Power Planning, Deep sub-micron technology issues, Floor Planning, Signal integrity analysis, Place And Route
Skills:
power integrity , Timing Closure, Process node design rules, Physical Design methodologies, Cadence toolchain, Signal Integrity
Skills:
Ecos, Perl, Tcl, Python Scripting, Sta, CTS, Cadence Innovus, routing optimization, congestion optimization, SDC, MMMC, advanced technology nodes, full-chip physical implementation, constraint development, floorplanning, PPA improvements, Timing Analysis, setup hold closure, SI crosstalk, Timing Closure, complex SoC designs, Placement, Power Planning