Layout Design Engineer
Layout Design Engineer
smartsoc solutions pvt ltd4-12 Years
- Posted 8 days ago
- Be among the first 10 applicants
Job Description
About the job
About the Company
SmartSOC Solutions is dedicated to delivering cutting-edge semiconductor solutions. Our mission is to innovate and excel in the field of advanced technology, fostering a culture of collaboration and excellence.
Qualifications
- 4 to 12 years of relevant experience in Analog Layout Design.
- Mandatory: Hands-on experience with FinFET technology or Samsung Foundry process technologies.
- Strong experience in advanced technology nodes such as 2nm, 3nm, 5nm, or 7nm.
- Experience in custom analog layout, DRC/LVS/ERC/PEX closure, and layout optimization.
- Immediate joiners or candidates who can join within a short notice period are preferred.
Responsibilities:
- Develop high-quality full-custom analog and mixed-signal layouts.
- Perform floorplanning, device matching, routing, shielding, and optimization for analog circuits.
- Execute layout verification including DRC, LVS, ERC, and PEX closure.
- Ensure layout quality while meeting performance, power, area, and reliability requirements.
- Collaborate with circuit designers to resolve layout-related issues and optimize design performance.
- Work with advanced process technologies including FinFET nodes (2nm, 3nm, 5nm, and 7nm).
- Perform parasitic-aware layout optimization and support post-layout verification.
- Ensure compliance with foundry design rules and best layout practices.
- Participate in design reviews and contribute to silicon bring-up support when required.
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
About Company
Skills:
cadence schematic capture , Verification tools - CALIBRE, Cadence Tools, Memory layout design, AI automation in layout, ElectroMigration, Hercules, SKILL Programming, Physical verification LVS, ERC, DRC, Script Programming, Antenna, Chip Integration, Floor-planning, Hierarchy layout
Skills:
Process design rules, Analog layout design, Design verification tools, Layout methodologies, Voltage drop, Micro-floor planning, Ir, Floorplans, Signal planning, Esd, TSMC N3 technology, Electron migration, High speed SerDes layouts, Power grid
Skills:
Perl, Python, Tcl, Skill, Calibre PVS, Cadence Virtuoso, High-voltage process technologies, IR drop, Physical verification tools, PEX, Reliability-aware layout, Antenna density, High-current routing, Layout methodology improvements, LVS, Parasitic control, Latch-up prevention, Electromigration, Noise isolation, Thermal effects, ERC, DRC, Extraction and reliability tools, Tape-out readiness, Guard rings
Skills:
CMOS Circuits, Mentor Calibre, Cadence PVS, LVS, tape-out, productivity-enhancing tools, chip-level floorplanning, ERC, chip-level integration verification, DRC, design scripts, Cadence Virtuoso, BiCMOS circuits, analog block integration, Layout Design