cadence schematic capture , Verification tools - CALIBRE, Cadence Tools, Memory layout design, AI automation in layout, ElectroMigration, Hercules, SKILL Programming, Physical verification LVS, ERC, DRC, Script Programming, Antenna, Chip Integration, Floor-planning, Hierarchy layout

Process design rules, Analog layout design, Design verification tools, Layout methodologies, Voltage drop, Micro-floor planning, Ir, Floorplans, Signal planning, Esd, TSMC N3 technology, Electron migration, High speed SerDes layouts, Power grid

Perl, Python, Tcl, Skill, Calibre PVS, Cadence Virtuoso, High-voltage process technologies, IR drop, Physical verification tools, PEX, Reliability-aware layout, Antenna density, High-current routing, Layout methodology improvements, LVS, Parasitic control, Latch-up prevention, Electromigration, Noise isolation, Thermal effects, ERC, DRC, Extraction and reliability tools, Tape-out readiness, Guard rings

CMOS Circuits, Mentor Calibre, Cadence PVS, LVS, tape-out, productivity-enhancing tools, chip-level floorplanning, ERC, chip-level integration verification, DRC, design scripts, Cadence Virtuoso, BiCMOS circuits, analog block integration, Layout Design