Routing, floorplanning, Physical Design, Sign-off, Placement, PNR, Timing Closure, CTS, Sta

C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation

Tcl, Python, Logical Equivalence, Synthesis, Timing Analysis, Physical Verification DRC LVS ERC, Physical design flows, Place And Route, EDA Tools, Budgeting, floorplanning, Clock CTS

power integrity , Routing, Synthesis, Multi-Voltage Domains, Sign-off, Physical Design implementation, Placement, Low-Power Design, Physical Verification, Timing Closure, floorplanning, CTS

Tcl, Python, PERL, ECO Timing Closure, Synthesis, Layout Closure, Block-level and Full-chip Floor-planning, primetime, Ir, Physical Verification, Innovus, CTS, Sta, ICC2, Physical Design, Tempus, RTL2GDSII flow, Seahawk, Place And Route, Timing Convergence, High Frequency Design Methodologies

Tcl, Routing, Perl, 28nm and lower technology nodes, Timing Constraints, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, Methodologies, CTS, Innovus, Sta, ICC2, Tk, Placement, Timing Closure, PT-PX, sub-micron technology, Netlist2GDSII Implementation

Network-on-Chips (NoC, Multi-mode multi-corner (MMMC timing closure, Physical design implementation, Synthesis, System IP components, Timing Closure, Sign-off, Coherent CPU clusters, floorplanning, Uncore subsystems, Place-and-route, Partitioning, RTL-to-GDSII implementation, Timing budgeting, Hierarchical design techniques