Object Oriented Programming, Shell, Perl, Python, Make file, Power aware verification, Gate-Level Simulation, System Verilog UVM, Mentor, Cadence, UPF, C based and assembly level testcases, Assertions, System Verilog Testbench Architecture, HDL such as Verilog SystemVerilog, Processor Architecture, Processor Verification, HVL such as SystemVerilog testbench OVM UVM, TCI, Synopsys, formal verification, Digital Design

Emulation, SoC design methodology, silicon bring-up, Microarchitecture, Timing Analysis, Synthesis, Physical Design, RISC CPU IP, Verification, Rtl Design

Tcl, Python, Perl, Innovus, Physical Formal Verification, Cross-Functional Collaboration, LEC, primetime, EDA Tools, Fusion Compiler, Calibre, Red Hawk, Tempus, Timing Closure STA, RTL-to-GDSII Execution, Programming Scripting, VCLP, PPA Optimization

manufacturing support , Routers, 100G Ethernet systems, SerDes interfaces, Hardware debugging, Timing synchronization, root-cause analysis, DDR memory subsystem design, PCIe PAM4 signaling technologies, High-speed Ethernet switches, PCB design validation, clock distribution systems

C, Simulation, CPU verification, Uvm, RTL, Emulation, Digital Design