Sr Staff Engineer, Hardware Design
Sr Staff Engineer, Hardware Design
SiMa.ai- Posted 14 days ago
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Job Description
Description
Job Title: Sr Staff Engineer, Hardware Design
Job Location: Bangalore, India (This position requires a full-time, on-site presence in our Bangalore, India Office)
Job ID: AI2552
Job Description
SiMa.ai is looking for an experienced hardware design engineer to own and evolve the RISC CPU IP used in our MLSoC™. You will work with architecture, verification, emulation, and physical design teams to define the microarchitecture, implement RTL, and make the modifications needed to meet performance, functionality, and SoC integration requirements.
You will contribute across the IP development lifecycle, from architecture and design reviews through synthesis, timing analysis, verification support, physical design collaboration, and silicon bring-up.
Responsibilities
Job Title: Sr Staff Engineer, Hardware Design
Job Location: Bangalore, India (This position requires a full-time, on-site presence in our Bangalore, India Office)
Job ID: AI2552
Job Description
SiMa.ai is looking for an experienced hardware design engineer to own and evolve the RISC CPU IP used in our MLSoC™. You will work with architecture, verification, emulation, and physical design teams to define the microarchitecture, implement RTL, and make the modifications needed to meet performance, functionality, and SoC integration requirements.
You will contribute across the IP development lifecycle, from architecture and design reviews through synthesis, timing analysis, verification support, physical design collaboration, and silicon bring-up.
Responsibilities
- Own the RISC CPU core and drive its design, integration, and ongoing development.
- Work with the architecture team to define and refine the CPU microarchitecture.
- Modify and optimize the RISC CPU RTL to meet performance, functionality, and SoC integration requirements.
- Review RTL and design changes for quality, correctness, and maintainability.
- Perform or support synthesis, static timing analysis, equivalence checking, CDC analysis, and linting.
- Work with verification and emulation teams to resolve issues and support test and debug activities.
- Collaborate with physical design teams on floor planning, timing closure, and other implementation needs.
- Support IP integration, chip validation, bring-up, and characterisation.
- Coordinate with the ML accelerator and SoC teams to ensure the RISC CPU IP meets system-level requirements.
- Improve design methodology and flows for CPU IP development.
- Bachelor's or master's degree in electrical engineering, computer engineering, or a related field.
- 8-11 years of professional experience in hardware IP design, SoC design, or a related area.
- Strong understanding of CPU architecture and experience developing or maintaining CPU IP.
- Experience with RTL design and SoC design methodology.
- Experience working across relevant parts of the design lifecycle, such as microarchitecture, synthesis, timing analysis, verification, emulation, physical design, or silicon bring-up.
- Experience with RISC CPU cores is plus.
- Experience with ARM CPUs and associated bus protocols.
- Experience integrating CPU IP into an SoC or working with accelerator-based systems.
- Takes ownership and follows through on commitments.
- Focuses on execution and results.
- Works effectively across teams and communicates clearly, including during difficult technical discussions.
- Demonstrates integrity, curiosity, and a collaborative approach.
More Info
Key Skills
SoC design methodology
silicon bring-up
RISC CPU IP
About Company
Skills:
Object Oriented Programming, Shell, Perl, Python, Make file, Power aware verification, Gate-Level Simulation, System Verilog UVM, Mentor, Cadence, UPF, C based and assembly level testcases, Assertions, System Verilog Testbench Architecture, HDL such as Verilog SystemVerilog, Processor Architecture, Processor Verification, HVL such as SystemVerilog testbench OVM UVM, TCI, Synopsys, formal verification, Digital Design
Skills:
static timing analysis, RISC CPU IP, CPU microarchitecture, IP integration, Floor Planning, silicon bring-up, Timing Analysis, Emulation, Physical Design, chip validation, Rtl Design, CDC analysis, ARM CPUs, SoC design methodology, characterisation, Synthesis, linting, Timing Closure, Verification, equivalence checking, BUS Protocols
Skills:
Tcl, Python, Perl, Innovus, Physical Formal Verification, Cross-Functional Collaboration, LEC, primetime, EDA Tools, Fusion Compiler, Calibre, Red Hawk, Tempus, Timing Closure STA, RTL-to-GDSII Execution, Programming Scripting, VCLP, PPA Optimization
Skills:
manufacturing support , Routers, 100G Ethernet systems, SerDes interfaces, Hardware debugging, Timing synchronization, root-cause analysis, DDR memory subsystem design, PCIe PAM4 signaling technologies, High-speed Ethernet switches, PCB design validation, clock distribution systems
Skills:
C, Simulation, CPU verification, Uvm, RTL, Emulation, Digital Design