power integrity , Tcl, Python, Perl, Sta, EM IR analysis, primetime, Tempus, Cadence Innovus, Voltus

production readiness , Verification, Floor Planning, Low Power Verification, Physical Design, Silicon Bring-up, Rtl Design, Placement, PnR Implementation, ASIC Design, power analysis, Design Reviews

Logic Design, Physical verification tools, floorplanning, RTL to GDS development, Physical design flows, Physical design optimization

Logic Design, Physical design architecture, P R Timing and Physical verification tools, floorplanning, Physical implementation flows, Physical design flows

Synthesis, physical verification closure, Formal, Timing Closure, block chip level implementation from Netlist to GDS, scripting skills – TCL

power optimization , FPGA Design, floorplanning, Place And Route, Timing Analysis, DRC/LVS Checks, Signal Integrity, Physical Verification, RTL Synthesis, Circuit Layout

Tcl, Python, Perl, IP integration, advanced process nodes, ECO generation, DFT timing modes, GLS enablement, Sta