Electrical Rule Checking (ERC), Design Rule Checking (DRC), Layout Versus Schematic (LVS), Custom Physical Routing, Analog Layout, Placement, Sub-8nm Advanced Process Nodes, FinFET, Floor Planning, Sram, Memory Structures

Global Product Development System (GPDS), Design for Six Sigma (DFSS), Verification And Validation, System Integration, Design for Manufacturability, Iso 13485, Fmea, FDA QSR, Design to Cost

Calibre DRC, LVS, Cadence Virtuoso

clocking , Design Reviews, Transistor-level Analog IC Circuit Design, Circuit Architectural Design, Prototype Chip Testing, Analog Circuit Layout, Manufacturing Test Plans, Analog Design, Data Converters, PMUs

Tableau, Excel, Data Visualization, Power Bi, Statistical Analysis, Control Plans, Jmp, Iso 9001, Reliability Testing, Fmea, Spc, quality engineering, 8D, Process Validation, Capa, Msa, FAI audit methods, Rca

MATLAB, high-speed SerDes, Ads, post-silicon validation, system level serial link analysis, performance optimization, Simulation, SerDes architectures