Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

C, Perl, Python, Fpga, Emulation platforms, Uvm, systemverilog, AMBA bus protocols, Transaction level modeling, Automation scripts, RTL

Verilog, Scripting Languages, Verification Tools, VHDL, Uvm, formal verification, Simulators

Shell, Perl, Python, Tcl, Debugging RTL verification issues, Assertions SVA, SoC IP architecture and verification methodologies, UVM methodology, systemverilog, Functional Verification, Coverage-driven verification

cache coherency , Uvm, DMA engines, ARM-based SoCs, memory systems, systemverilog, Transaction-level verification, CHI, Ace, AXI NoC architectures

simvision , python, Cadence simulation tools, Uvm, Xcelium, netlist simulation

Perl, Vcs, Python, Tcl, Uvm, Verdi, Questa, systemverilog

bandwidth management , Machine Learning, Artificial Intelligence, SystemVerilog Assertions, Specman E, Debug, formal tools, IP subsystem SoCs, congestion control, AI ML accelerators, systemverilog, memory system architecture, vector processing units, ASIC standard interfaces, packet processing, Verification, Universal Verification Methodology