Verilog, Tcl, Python, Perl, Git, MBIST, analog test solutions, DFT architectures, systemverilog, ATPG, LBIST

Perl, Python, Tcl, CDC Lint, low power design, digital circuit design principles, RDC, Timing Analysis Concepts, RTL design synthesis, UPF

Verilog, Microprocessors, LINT, low power design, cdc, Design Compiler, Timing concepts for ASIC, Memory controller designs, ASIC RTL Design, primetime, Asynchronous interface, Synthesis, RTL Coding, Logic design micro-architecture, System-Verilog

Soc Architecture, System Verilog, scoreboarding, digital design fundamentals, verification concepts, simulation logs, Uvm, ASIC SoC functional verification, waveform tools, constrained-random stimulus, BUS Protocols, assertions, SVA, functional coverage

Pvs, Perl, Python, Tcl, pegasus, LVS, Voltus, DRC, QRC, EM and thermal analysis platforms, Quantus, Thermal analysis concepts and extraction methodologies, Automated engineering workflows

Verilog, System Verilog, AI-powered tools, Timing Closure, EDA design processes, ASIC Design, Simulation and debugging, Functional verification tools, Synthesis tools