Sr. RTL (ASIC) Design Engineer
Sr. RTL (ASIC) Design Engineer
ALTEN Calsoft Labs- Posted 11 hours ago
- Be among the first 10 applicants
Job Description
Job Description
Experience: 5 to 8 Years
Location: Bangalore / Hyderabad
Expertise should include and not limited to the following
- Strong understanding of digital circuit design principles and timing analysis concepts
- Experience with RTL design, synthesis
- Experience with CDC , Lint , RDC, Low power design /UPF
- Proficiency in scripting languages like TCL, Perl, or Python for automation
- Excellent problem-solving and debugging skills
- Strong communication and teamwork abilities to collaborate with cross-functional teams
More Info
Key Skills
CDC Lint
digital circuit design principles
RDC
RTL design synthesis
UPF
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