Vcs, Pcie, Python, Tcl, Xcelium, Uvm, systemverilog, APB, Questa, AXI4, AHB, SVA

Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage

C, Perl, Python, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, systemverilog, Industry standard I/O interfaces, AMBA bus protocols, RTL development environments, Baremetal processor environments, Formal verification methods, UPF based low power verification, Transaction level modeling

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

display technologies , Python Programming, Functionality, Bit Depth Color, OS Ecosystems, Bitstream Verification, MIPI DSI-2, Introspect SV series systems, FPGA platforms, Scaling Processing, PVT Testing, Frame Buffer, Lab Instrumentation, Pixel Formats, SV UVM, Low-Level Software, Continuous Integration tools

Verilog, Scripting Languages, Verification Tools, VHDL, Uvm, formal verification, Simulators

Test Plan Creation, Debugging, Python, Perl, VIP integration, testbench architecture, Uvm, verification methodologies, scoreboarding, systemverilog, coverage-driven verification, execution and review, assertions, regression management, debug flows, functional coverage

Shell, Perl, Python, Tcl, Debugging RTL verification issues, Assertions SVA, UVM methodology, Coverage-driven verification, systemverilog, Functional Verification

Spi, I2c, Gpio, Uart, Pcie, DDR, UVM methodology, I3C, QSPI, CXL, systemverilog, HBM