Cadence Tools, Gate level simulations, VHDL, Formal verification methodologies, VAMS, Testbench creation, Uvm, systemverilog, Motor control for BLDC BSM motor driver devices

SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification

Vcs, Pcie, Python, Tcl, Xcelium, Uvm, systemverilog, APB, Questa, AXI4, AHB, SVA

C, Perl, Python, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, systemverilog, Industry standard I/O interfaces, AMBA bus protocols, RTL development environments, Baremetal processor environments, Formal verification methods, UPF based low power verification, Transaction level modeling

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Verilog, Scripting Languages, Verification Tools, VHDL, Uvm, formal verification, Simulators

Vcs, Shell, Perl, Python, Verdi, Assertions SVA, Verification planning, RISC-V, Regression and debug, UVM testbenches, Uvm, systemverilog, Test-plan development, Functional and code coverage, DDR verification, Questa

Perl, Tcl, Python, Uvm, MIPI DSI, systemverilog, HDMI, DisplayPort