Nvme, SAS, Silicon Validation, Pcie, physical implementation, Synthesis, tape-out processes, RTL design using Verilog, Uvm, systemverilog, Dft, Timing Closure, CXL

Tcl, Python, Perl, CI CD integration, assertion-based verification, CAD tool integration, coverage analysis, Uvm, regression automation, formal verification, systemverilog, dynamic verification

Sta, cdc, LINT, power analysis, UPF, Dft, RDC, Low Power design techniques, RTL coding techniques, Synthesis, Digital physical implementation, Place-and-route

biostatistics , cdms , Ml, Hl7, SAS, Python, Sycamore, Medidata Rave, Domino, Ai, GenAI, ctms, epro, Oracle InForm, EDC Platforms, USDM, SAS Viya, statistical programming, LSAF, Clinical Data Management, Nurocor, FHIR, R, Clinical Data Standards, Formedix, eClinical Elluminate, eTMF, Oracle LSH, Veeva EDC

Peripheral subsystems, Assertions, UVM-based test plan development, HSIO, SoC-level verification, Integration of multiple IPs, Verification infrastructures, coverage analysis

Silicon Validation, Soc Architecture, Physical Design, manufacturing, digital design verification, Dft

Ecos, Clock Reset UPF, FCR ECR reviews, RTL construction, SoC DV test plans, PPA targets, Fuse Documentation, SOC design, constraint and timing convergence, IP integration

Ecos, SoC DV test plans, RTL construction, FCR ECR reviews, PPA targets, SOC design, Fuse Documentation, Clock Reset UPF, constraint and timing convergence, IP integration