UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), C, C++, Shell, Pcie, Perl, Arm, Python, Tcl, Systemc, MCU, Hardware Emulation Platforms, RISC-V, UCIe, systemverilog, Verification Methodology, AMBA, Axi, Formal Model Equivalence Checking Tools, formal verification, VC Formal

Shell, PERL, Fc, Python, Tcl, Cadence LEC, Mentor Calibre, Apache Redhawk, Synopsys DC, Cadence Innovus, Primetime-DMSA, Synopsys Formality, Synopsys ICV, Synopsys ICC2

Sta, Resource Planning, floorplanning, RTL-to-GDSII implementation flow, CTS routing, Physical Verification, ODC operations, SoC implementation, Timing Closure, Physical design sign-off, Physical Design, EDA Tools, Placement, Team Development, PPA optimization

clocking , Verilog, EDA tools for synthesis, LINT, Use of AI for design, cdc, SoC-level design and integration, Synthesis flows, Rtl Design, spyglass, VHDL, Verification methodologies, RDC, Digital design principles, Resets, Timing Constraints, Micro-architecture design, Low-power design techniques, Timing Analysis

bedrock , S3, Machine Learning, Cloud Infrastructure, Tensorflow, API Design, Data Science, Lambda, Pandas, Pytorch, ECS, Python, AWS, Generative AI, Step Functions, scikit-learn, MLflow, EKS, SageMaker

IR EM Analysis, SI PI Analysis, Floorplanning and Power Planning, Physical Verification, STA and Timing Closure, Low Power Design UPF CPF, Physical Design and Signoff, Tcl Python Scripting, Advanced Node Design Methodologies, Clock Architecture and CTS, AI-assisted Design Flows

Model Context Protocol (MCP), Retrieval-Augmented Generation (RAG), Large Language Models (LLMs), Typescript, Javascript, Python, Testing Frameworks, AWS cloud services, AI agents, Prompt engineering, AI system design, Vector databases, and engineering management tools, Agile environments, Collaboration, Responsible AI practices, Modern planning, CI/CD pipelines, AI observability, Cloud-native applications

Shell, Perl, Python, Tcl, Ecos, Flows, automation, Innovus, primetime, ICC2, Tempus, FusionCompiler, Design Reviews, EM closure, Ir, PD methodologies, tapeout readiness, RTL-to-GDSII flow, Timing Closure, Si, PPA optimization

Scripting, EDA Tool Proficiency, Cross-Functional Collaboration, Risk Issue Management, Team Leadership Mentorship, SerDes IP Integration, Architecture Methodology, Technical Ownership Project Planning, RTL-to-GDSII Execution, Advanced Technology Nodes, Stakeholder Vendor Alignment, Timing PPA Closure, SoC-Level Physical Design

python, Microstation, pavement alignment, highway and development infrastructure design, digital workflows automation, Bentley ORD, drainage utilities, Civil cell