Quality Assurance, Circuit Design, Layout Automation Techniques, MOSFET Electrical Behavior, Transistor-Level Device Physics, Standard Cell Layout Design, Layout Methodologies, Characterization Modeling, CMOS Design Principles, Standard Cell EDA Views, PPA Performance, SPICE Circuit Simulators

cadence spectre , Python, Analog Mixed Signal Verification, Skill, Xcelium, SystemVerilog-RNM, Uvm, Model vs Schematic Comparison, High-speed Design AMS Verification, Behavioral Modelling, Synopsys VCS FineSim, Verilog-AMS, AMS Designer, Synopsys AMS tools, Cadence Virtuoso, Mixed Signal Modelling, SerDes Verification

cadence schematic capture , Cadence Tools, Memory layout design, AI automation in layout, CALIBRE, ElectroMigration, Hercules, SKILL Programming, Physical Verification, LVS, ERC, DRC, Script Programming, Antenna, Chip Integration, Floor-planning, Hierarchy layout

Perl, Python, Tcl, Skill, Calibre PVS, Cadence Virtuoso, High-voltage process technologies, IR drop, Physical verification tools, PEX, Reliability-aware layout, Antenna density, High-current routing, Layout methodology improvements, LVS, Parasitic control, Latch-up prevention, Electromigration, Noise isolation, Thermal effects, ERC, DRC, Extraction and reliability tools, Tape-out readiness, Guard rings

Layout optimization, Samsung Foundry process technologies, ERC, PEX closure, LVS, Analog Layout Design, Custom analog layout DRC, FinFET technology

cdegs , bill of materials , Land Utilisation Plan, Design Calculations, EHV Projects, WinIGS, Lighting and Lightning Protection, Grounding Layout, Electrical Engineering, Conduit Layouts, Substation Design, Busbar Sizing