layout verification , Java, Scripting Languages, Python, BCD technologies, Mentor, Cadence, FinFET technologies, planar CMOS, EDA Tools, Analog Mixed Signal modules, Synopsys

parasitic optimizing, CADENCE layout entry tools, layout methodology, CALIBRE DRC ERC LVS

Tcl Scripting, Routing, Python, Layout violation resolution, floorplanning, Physical Verification, EM closure, Synopsys Fusion Compiler, Cadence Innovus, Physical design flows, Signal integrity analysis, Dfm, Timing Closure, Placement, Clock Tree Synthesis

Ant, UNIX, Linux, Perl, Python, Tcl, LPE, Calibre ICV, LVS, Esd, ERC, C-shell, DRC

Tcl Scripting, Routing, Python, floorplanning, Layout violation resolution, Physical Verification, EM closure, Cadence Innovus, Synopsys Fusion Compiler, Physical design flows, Signal integrity analysis, Dfm, Timing Closure, Placement, Clock Tree Synthesis

CADENCE layout entry tools, ERC, CALIBRE DRC, LVS, Synopsys, Cadence Virtuoso

System Verilog, Synopsys, UVM verification methodology, Cadence

Perl, Skill, CADENCE layout entry tools, ERC, Ample, LVS, CALIBRE DRC, Synopsys, Cadence Virtuoso