Electrical Rule Checking (ERC), Design Rule Checking (DRC), Layout Versus Schematic (LVS), Custom Physical Routing, Analog Layout, Placement, Sub-8nm Advanced Process Nodes, FinFET, Floor Planning, Sram, Memory Structures

Ant, Analog layout design, Isolation techniques, Mentor Calibre, LVS, Signal and clock shielding, Latch-up, EMIR, CMOS circuit theory, ERC, Esd, DRC, Layout design and verification, Cadence Virtuoso, Reliability

DDR, Pcie, Ethernet, Sata, ADC, FinFET-node design, BGR, Analog Circuit Design, Pll, Layout Design, MIPI, LDO, Opamp, high-speed interface designs

clocking , shielding , whiteboarding , matching , Prototype chip bring-up and testing, Validation, Manufacturing test plans, floorplanning, Production test support, Tape-out, Data converters, LVS, Probe access trim structures, Analog IC layout, Transistor-level analog IC layout, Layout design reviews, DRC, PMUs, Circuit design reviews, Parasitic-sensitive structures, Parasitic Extraction, Parasitic extraction LVS DRC antenna and fill closure