Ant, Mentor Calibre, LVS, Latch-up, signal and clock shielding, EMIR, CMOS circuit theory, Esd, ERC, DRC, isolation techniques, analog layout design, Cadence Virtuoso, Reliability

Ant, Mentor Calibre, LVS, Latch-up, EMIR, CMOS circuit theory, Esd, ERC, DRC, isolation techniques, analog layout design, clock shielding, Cadence Virtuoso, Reliability

Perl, Verilog, Python, silicon debug, Synopsys VCS, NAND Validation, Electrical Failure Analysis, AI ML techniques

Java, Unix, CGI, HTML, Perl, Python, Component Testing, Cadence, fabrication process, DRAM operation, semiconductor device physics, advanced packaging, DFII, wafer testing, module testing

Perl, Cadence Virtuoso, CALIBRE DRC, Synopsys, CADENCE layout entry tools, LVS, ERC, Skill, Ample

Ruby, Java, Windows, Usb, Shell, Linux, Python, Pcie, Perl, DDR, SoC design system integration, x86 CPU GPU architecture, HSIO, debugging at system level

layout verification , Java, Python, Scripting Languages, Synopsys, planar CMOS, BCD technologies, EDA Tools, Analog Mixed Signal modules, FinFET technologies, Mentor, Cadence