Ant, Mentor Calibre, LVS, Latch-up, signal and clock shielding, EMIR, CMOS circuit theory, Esd, ERC, DRC, isolation techniques, analog layout design, Cadence Virtuoso, Reliability

CADENCE layout entry tools, Synopsys, Cadence Virtuoso, CALIBRE DRC ERC LVS

Python, primetime, Synopsys Design Compiler, Tcl Shell, Formality, VCLP, Synopsys Fusion Compiler, Cadence Genus, VC SpyGlass

layout verification , Java, Python, Scripting Languages, Synopsys, planar CMOS, BCD technologies, EDA Tools, Analog Mixed Signal modules, FinFET technologies, Mentor, Cadence

Ant, Mentor Calibre, LVS, Latch-up, EMIR, CMOS circuit theory, Esd, ERC, DRC, isolation techniques, analog layout design, clock shielding, Cadence Virtuoso, Reliability

regulators , receivers , Dac, Python Scripting, mixer, Oscillators, Temp Sensors, Transmitters, Pa, RF General, bandgaps, submicron CMOS technologies, RF modules, Dfm, parasitic reduction, linear switched ADC, VCO, Amplifiers, LNA, Cadence Virtuoso VXL, Mentor Calibre, Analog Mixed Signal Design, Esd, Analog Layout, Pll

Backend Development, Java, Rust, DEFI, SUI, Go, Aptos, Blockchain fundamentals, Web3, Solana, ERC-4337

boundary scan , Perl, Linux Shell Scripting, Python, Tcl, DFT instruments, Synthesis, digital DFT design, MBIST, make, ASIC development, SSN, ATE test, occ, formal verification, EDA Tools, silicon failure analysis, EDT, TAP controller, logic simulation, LBIST