Ant, Mentor Calibre, LVS, Latch-up, signal and clock shielding, EMIR, CMOS circuit theory, Esd, ERC, DRC, isolation techniques, analog layout design, Cadence Virtuoso, Reliability

Perl, Cadence Virtuoso, CALIBRE DRC, Synopsys, CADENCE layout entry tools, LVS, ERC, Skill, Ample

Python, primetime, Synopsys Design Compiler, Tcl Shell, Formality, VCLP, Synopsys Fusion Compiler, Cadence Genus, VC SpyGlass

layout verification , Java, Python, Scripting Languages, Synopsys, planar CMOS, BCD technologies, EDA Tools, Analog Mixed Signal modules, FinFET technologies, Mentor, Cadence

Ant, Mentor Calibre, LVS, Latch-up, EMIR, CMOS circuit theory, Esd, ERC, DRC, isolation techniques, analog layout design, clock shielding, Cadence Virtuoso, Reliability

regulators , receivers , Dac, Python Scripting, mixer, Oscillators, Temp Sensors, Transmitters, Pa, RF General, bandgaps, submicron CMOS technologies, RF modules, Dfm, parasitic reduction, linear switched ADC, VCO, Amplifiers, LNA, Cadence Virtuoso VXL, Mentor Calibre, Analog Mixed Signal Design, Esd, Analog Layout, Pll

CADENCE layout entry tools, layout methodology, CALIBRE DRC ERC LVS

redhawk , Static Timing Analysis, primetime, Quantus, Crosstalk Analysis, EM IR-Drop, Tempus, Cadence Innovus, Synopsys Fusion Compiler, LVS, Voltus, Calibre, Extraction, Physical Design, StarRC, EDA Tools, ERC, DRC, Antenna, PTSI