Vc, Perl, Verilog, Python, System Verilog, Tcl, LINT, cdc, Vlsi, front-end design verification techniques, formal verification tools, LEC, spyglass, FV, Synthesis, RDC, Design Compilers, EDA Tools, ASIC Design

Place and route (PnR), System on Chips (SoCs), Static Timing Analysis (STA), Unified Power Format (UPF), Deep sub-micron technology, Multi-voltage domains, Physical design methodologies, Circuit Design, Power gating, IP integration, Netlist2GDS, ASIC design flows, Sign-off optimizations, Multiple technology nodes in advanced processes, device physics, Floorplan, Sign-off convergence, Lower technology nodes, Low power design implementation

Perl, Python, Tcl, Statistical Analysis, SPICE simulations, PVT corners, transistor-level simulation, yield optimization, Cadence Virtuoso, SRAM Memory circuit design

power optimization , Routing, Logic Design, Perl, Python, Tcl, Circuit Design, floorplanning, Mentor, Cadence, Signal Integrity, LVS, Digital Design Fundamentals, Physical Verification, Physical Design, ERC, Placement, Timing Closure, DRC, Timing, EDA Tools, Synopsys, Rtl Design

Python, Tcl, Logical design, Digital design flows, systemverilog

Coding Methodology, RTL Linting, Synthesis, Design Compiler, primetime, Timing Closure, Genus, SDC Constraints, Tempus, systemverilog

redhawk , Python Scripting, Pvs, Perl, Tcl, QRC, primetime, ICC2, Tempus, Voltus, Innovus, Calibre, Physical Design, Starrcxt

Perl, Verilog, Python, Uvm, SVA, systemverilog

Java, C, multithreading, Python, AI tools, LSF concepts, debugging skills, EDA flow Automation, multiprocessing