Ecos, Perl, Tcl, Python Scripting, Sta, CTS, Cadence Innovus, routing optimization, congestion optimization, SDC, MMMC, advanced technology nodes, full-chip physical implementation, constraint development, floorplanning, PPA improvements, Timing Analysis, setup hold closure, SI crosstalk, Timing Closure, complex SoC designs, Placement, Power Planning

hardware engineering , Clock Tree Synthesis (CTS), Unix, Perl, Linux, Low power verification, floorplanning, Placement, power analysis, PNR implementation, CTS optimization, Optical systems, Equipment and packaging test systems, DSP systems

power optimization , FPGA Design, floorplanning, Place And Route, Timing Analysis, DRC/LVS Checks, Signal Integrity, Physical Verification, RTL Synthesis, Circuit Layout

power integrity , Routing, CTS, floorplanning, Low-Power Design, Synthesis, Physical Verification, Timing Closure, Placement, Sign-off, Multi-Voltage Domains, Physical Design implementation

synopsys tools , Tcl Scripting, Asic Physical Design, place-and-route, IC Compiler, Timing Closure, Design Compiler, Fusion Compiler, sign-off, Power Planning, floorplanning

power optimization , static timing analysis, routing, Verilog, Synthesis, power distribution analysis, submicron process node technologies, power delivery methodologies, Power Estimation, reliability verification, formal verification, VHDL, Placement, low-power design techniques, timing signoff, Clock Tree Synthesis

redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus