Place and route (PnR), System on Chips (SoCs), Static Timing Analysis (STA), Unified Power Format (UPF), Deep sub-micron technology, Multi-voltage domains, Physical design methodologies, Circuit Design, Power gating, IP integration, Netlist2GDS, ASIC design flows, Sign-off optimizations, Multiple technology nodes in advanced processes, device physics, Floorplan, Sign-off convergence, Lower technology nodes, Low power design implementation