Yield Process Engineer

Who We Are

Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips - the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world - like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world.

What We Offer

Location:

Singapore,SGP

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As a Process Engineer, you'll play a crucial role in designing and optimizing manufacturing processes for display and semiconductor manufacturing technologies. You will collect and analyze data, perform hardware characterization, and troubleshoot engineering issues. You'll also measure film properties, generate technical documentation, and engage with customers to resolve concerns. Process Engineers collaborate with vendors and suppliers, and become familiar with implementing new technologies and products. You will experiment, learn, and collaborate with some of the brightest minds in the semiconductor and display industries, partnering with our globally recognized R&D teams on state-of-the-art research and development projects.

Position Summary

We are seeking a highly experienced Yield Development Engineer (YDD Engineer) to join our Photonics Platform Business Group. This role is responsible for driving yield learning and yield ramp for advanced semiconductor and photonic devices, enabling successful transition from R&D into scalable, highvolume manufacturing. The YDD Engineer will work closely with process integration, module, design, and manufacturing teams to identify yield limiters, implement corrective actions, and establish robust, manufacturable processes.

Key Responsibilities

• Lead yield development activities across early technology development, pilot runs, and highvolume manufacturing ramp.
• Identify, analyze, and eliminate yield limiters related to process variation, integration interactions, and design sensitivities.
• Define and execute yield-focused DOEs to characterize process windows, sensitivity drivers, and defect mechanisms.
• Perform detailed yield data analysis, including parametric, inline, defect, and final test data, to guide process improvements.
• Collaborate with process integration and module teams (lithography, etch, deposition, CMP, metrology) to close yield gaps.
• Drive root-cause analysis for systematic and random yield loss using statistical, physical, and failure analysis methods.
• Provide feedback to design teams on DFM / DfY (Design for Yield) opportunities and layout-related yield risks.
• Support technology transfer to high-volume manufacturing, ensuring yield performance meets business requirements.
• Establish yield monitoring strategies, control plans, and baseline metrics for sustained manufacturing performance.
• Contribute to yield ramp strategies and technology roadmaps, balancing performance, cost, and manufacturability.
• Mentor junior engineers and technicians on yield analysis tools, methodologies, and best practices.

Qualifications

• Master's degree or PhD in Electrical Engineering, Chemical Engineering, Materials Science, or a related field (PhD preferred).
• Minimum 5 years of industry experience, with 3+ years in yield development, process integration, or manufacturing yield engineering, preferably in highvolume semiconductor environments.
• Strong understanding of semiconductor fabrication processes and their impact on yield (lithography, etch, deposition, metrology).
• Demonstrated expertise in statistical yield analysis and process control, including DOE, SPC, JMP, and multivariate analysis.
• Experience correlating inline, defect, electrical, and optical test data to yield performance.
• Ability to read and interpret layout data (GDS, OASIS) familiarity with OPC and layout-related yield effects is a strong plus.
• Knowledge of photonics devices, optical components, and optical test methodologies is desirable.
• Strong communication skills with the ability to clearly present yield results and recommendations to crossfunctional and senior stakeholders.
• Highly organized and detailoriented, capable of managing multiple yield improvement efforts in parallel.
• Familiarity with semiconductor manufacturing standards and best practices (ISO, SEMI, ITAR) and basic project management skills are a plus.

Functional Knowledge

• Recognized as a technical expert in yield development and yield learning methodologies.
• Demonstrates deep expertise in own discipline with strong understanding of upstream and downstream process interactions.

Business Expertise

• Anticipates yield, cost, and manufacturability risks proactively recommends yield improvement and riskmitigation actions.

Leadership

• Leads yield improvement initiatives involving high technical complexity and crossfunctional coordination.
• Defines execution strategies for yield ramp and yield recovery programs.

Problem Solving

• Solves complex, nonobvious yield problems with significant business impact using analytical, statistical, and creative approaches.

Impact

• Influences technology readiness, manufacturing ramp decisions, and resource prioritization through yield performance outcomes.

Interpersonal Skills

• Effectively communicates complex yield issues, anticipates concerns, and influences decisions at senior technical and management levels.

Additional Information

Time Type:

Full time

Employee Type:

Assignee / Regular

Travel:

Yes, 10% of the Time

Relocation Eligible:

No

Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.