Staff Layout Engineer

Job Description:

Job Description

Role Overview

Responsible for executing high-quality layouts across Standard Cells, I/O pads, and Mixed-Signal IP in advanced processes within project schedules.

Work location : Singapore

Key Responsibilities

• Layout Design & Execution: Apply design guidelines and advanced process rules to deliver high-performance, robust layouts.
• Planning & Floorplanning: Work independently to manage schedules and execute layouts from the transistor level up, including cell- and block-level floorplanning.
• Collaboration & Innovation: Adapt quickly to emerging layout methodologies, adopt new ideas, and communicate effectively with engineers across all sites.
  
  

Skill Set & Requirements

• Education & Experience: Bachelor in Electronic Engineering with a minimum of 8 years of IC layout experience.
• Core Technical Expertise:
• Strong background in Standard Cell, Memory, Full Custom, and/or Analog/Mixed-Signal layout.
• Solid understanding of ESD and Latch-up principles for I/O design.
• Deep understanding of deep sub-micron / advanced nodes (e.g. 5nm, 3nm, 2nm, 1.4nm ).
• Domain & Tool Knowledge:
• Proficient with Cadence Virtuoso layout tool and Calibre physical verification (DRC, LVS, ERC, Antenna, and EM/IR analysis.)
• Scripting knowledge (Shell, Python, Tcl) or Cadence SKILL programming is a plus.
• Personal Attributes:
• Self-motivated, capable of working independently, and a strong collaborative team player.
• Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
• Good leadership quality on project management.
• Re-location:
• Must be available for immediate relocation to Singapore
  
  

R026694