Master's degree and/or PhD Preferred in Electrical Engineering or related fields with 2+ years of experience.
Should have strong analog design fundamentals and experience in designing analog circuit blocks such as PLL, Data Converters, Oscillators and high-speed SerDes blocks (CTLE, FFE, DFE, CDR, PLL, Line driver, etc.).
Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must
Knowledge of the fundamentals on signal integrity improvement, noise reduction and Multi-GHz low-jitter clock generation & distribution.
Good understanding of analog layouts in FinFet and its effect on high-speed designs
Experienced in system level pre-tape out analog validation
Experienced in lab chip bring-up and debugging efforts
Strong communication and documentation skills
Job Responsibilities
The candidate will be working on analog design of high-speed and high-performance SerDes in advanced technology nodes, 3nm, 2nm and beyond.
Participate in SerDes Architecture Development with DSP, Analog and Digital design teams.
Work with the AE for the IP characterization and validation plan
