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Silicon Design Engineer

Fresher
SGD 4,500 - 6,000 per month
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  • Posted 11 days ago
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Job Description

THE ROLE:

We are seeking a Static Timing Analysis (STA) Engineer to support the timing verification of our digital and mixedsignal designs. The successful candidate will work under the guidance of senior engineers to apply timing constraints, execute STA flows, and contribute to the development of robust design methodologies. This role requires close collaboration with crossfunctional teams and offers an opportunity to build strong STA fundamentals while supporting the delivery of highquality products.

THE PERSON:

You demonstrate a strong interest in modern, complex system architectures, digital design, and verification methodologies. You work effectively in collaborative environments and communicate clearly with team members and stakeholders. You apply analytical thinking and sound problemsolving skills to technical challenges, and you are committed to continuous learning and taking ownership of new and complex tasks.

KEY RESPONSIBILITIES:

  • Support static timing analysis for digital and mixed-signal designs, learning to apply industry best practices.
  • Use state-of-the-art EDA tools under guidance to analyze and improve timing performance.
  • Assist in developing and validating timing constraints to ensure the design meets performance and clocking requirements.
  • Work closely with design and layout engineers to help identify and resolve timing issues.
  • Prepare and maintain timing reports and related documentation used for reviews and sign-off.
  • Learn to evaluate and apply industry-standard modeling formats for timing analysis.
  • Participate in design reviews and contribute observations on timing-related topics as you build expertise.
  • Support the team in refining timing methodologies and workflows to enhance efficiency and accuracy.

PREFERRED EXPERIENCE:

  • A solid understanding of digital and mixed-signal design fundamentals, including timing and transistor behavior.
  • Familiarity with common industry formats such as Liberty, Verilog, LEF, and SPICE.
  • Interest in learning layout checks like DRC and LVS.
  • Exposure to STA or circuit simulation tools (e.g., PrimeTime, Tempus, HSPICE/SPECTRE) is beneficial, though not mandatory-you will learn on the job.
  • Ability to write simple scripts in Python, Perl, or TCL, or a willingness to learn these languages for automation tasks.
  • Ability and willingness to leverage AI tools to accelerate learning, automate routine tasks, and develop innovative solutions.
  • Strong curiosity, problem-solving mindset, and attention to detail.
  • Comfortable working collaboratively, asking questions, and communicating clearly in a team environment.
  • Self-motivated, eager to grow, and ready to take on new challenges in a fast-paced setting.

ACADEMIC CREDENTIALS:

  • Bachelors or Masters degree in computer engineering/Electrical Engineering

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Job ID: 144617483